1. Field of the Invention
The present invention relates generally to video encoder devices, and particularly, to a methodology for reducing power consumption in MPEG-2 compliant video encoder circuits.
2. Discussion of the Prior Art
Due to the amount of computations required, MPEG-2 hardware video encoders require many logic circuits, resulting in large amounts of power consumption. For instance, studies have demonstrated that clocks provided per functional unit of a device consume 41%-73% of the total average power consumed by that functional unit, largely due to the difference between the clock switching factor and the random logic switching. This large power requirement translates to a need for extra assistance with dissipating heat, which may require additional board space and more aggressive cooling techniques such as large heat sinks and more fans. Devices consuming large amounts of power thus require more carefully designed circuits, increasing the cost of the chip and printed circuit board, and the final product in which it is housed.
For example, in a typical video encoder, on-chip memory arrays are provided. In traditional implementations of on-chip array elements, a free running oscillator 11 is usually provided as the clock input to the array 10, as generally shown in FIG. l. Every transition of the oscillator results in the switching of a number of internal array nodes (the actual number being dependent on the design details of the array element itself) regardless of whether a read or a write was performed during the given cycle. For instance, transitions of array data and address lines between read/write cycle occur when the registers feeding the data and address lines of the on-chip array are fed with a free running (non-gated) oscillator and the data input to these registers changes for reasons other than prior to performing an array read/write. If the address register has a free running clock, each nodal transition in turn results in power dissipation.
Prior art techniques for reducing power consumption in electronic devices include the switching on/off of power supply voltages and/or clock signals to various devices when they are not used. U.S. Pat. No. 5,461,266 describes a typical technique for achieving reduced power consumption in computers by implementing a clock supply control device having the ability to stop or commence clock input to individual device components. However, the clock control device described in U.S. Pat. No. 5,461,266 implements a processor that requires many machine cycles to check the status of flags contained in an elaborate look-up table generated for tracking when a component has been brought to an unused condition before initiating stopping of the clock supply to that individual component.
It would be highly desirable to provide a computationally intensive video encoder such as an MPEG-2 video encoder with a power reduction methodology that is simple to implement, requiring minimal logic.
It would be further desirable to provide a methodology and apparatus for reducing power consumption of on-chip memory arrays in devices such as MPEG-2 compliant encoders.